The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to metrology for process control, such as end point determination.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface and planarizing the filler layer. For certain applications, the filler layer is planarized until the non-planar surface is exposed. A conductive filler layer, for example, can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs, and lines that provide conductive paths between thin film circuits on the substrate. For other applications, such as oxide polishing, the filler layer is planarized until a predetermined thickness is left over the non-planar surface. In addition, planarization of the substrate surface is usually required for photolithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is typically placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a standard pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically reactive agent, and abrasive particles if a standard pad is used, is supplied to the surface of the polishing pad.
One problem in CMP is determining whether the polishing process is complete, i.e., whether a substrate layer has been planarized to a desired flatness or thickness, or when a desired amount of material has been removed. Overpolishing (removing too much) of a conductive layer or film leads to increased circuit resistance. On the other hand, underpolishing (removing too little) of a conductive layer leads to electrical shorting. Variations in the initial thickness of the substrate layer, the slurry composition, the polishing pad condition, the relative speed between the polishing pad and the substrate, and the load on the substrate can cause variations in the material removal rate. These variations cause variations in the time needed to reach the polishing endpoint. Therefore, the polishing endpoint cannot be determined merely as a function of polishing time.
One way to determine the polishing endpoint is to remove the substrate from the polishing surface and examine it. By way of example, the substrate can be transferred to a metrology station where the thickness of a substrate layer is measured with a profilometer or a resistivity measurement. If the desired specifications are not met, the substrate is reloaded into the CMP apparatus for further processing. This reloading is a time-consuming procedure that reduces the throughput of the CMP apparatus. Alternatively, the examination might reveal that an excessive amount of material has been removed, rendering the substrate unusable.
More recently, in-situ monitoring of the substrate has been performed, for example, with optical or eddy current sensors, in order to detect the polishing endpoint. Other proposed endpoint detection techniques have involved measurements of friction, motor current, slurry chemistry, acoustics and conductivity.